Nanotubes are High Mobility Semiconductors

The electron transport properties of a very long (20 micron) CVD-grown nanotube are reported. In this device the transport is dominated by intrinsic scattering processes at room temperature. The room temperature hole mobility is 20,000 cm/Vs, exceeding that of technologically-relevant semiconductors. The mobility increases with decreasing temperature, and is estimated to be greater than 180,000 cm/Vs at 470 mK. Single-walled carbon nanotubes (SWNTs) are currently being considered for revolutionary applications in nanolectronics. While metallic SWNTs have been shown to conduct electrons ballistically over micron lengths at room temperature, the picture of electron transport in semiconducting SWNTs is less clear. Transport in semiconducting SWNTs synthesized via laser ablation has been previously interpreted as diffusive, with a low mobility (~20 cm/V·s) [1]. However electrostatic force microscopy (EFM) [2] and low temperature transport [3] measurements on similar devices indicate that the conduction is limited by a series of large transport barriers. EFM measurements on semiconducting SWNTs grown by chemical vapor deposition instead show diffusive conduction with a long mean free path. Here we study electron transport in a very long (20 micron) CVD-grown semiconducting nanotube, in which we expect the resistance to be dominated by intrinsic scattering processes in the nanotube, and not the contacts. An extremely high mobility is observed, 20,000 cm/V·s at room temperature, greatly exceeding the hole mobilities of current semiconductor MOSFETs. The mobility increases with decreasing temperature, indicating that a temperature-dependent scattering process dominates at room temperature. The nanotube studied here was synthesized by chemical vapor deposition (CVD) using a method adapted from Hafner et al. [4]: The starting substrate is degeneratelydoped silicon with a 500 nm oxide layer. Catalyst is deposited by dipping the substrate into a Fe(NO3)3/isopropanol solution followed by dipping in hexane to form Fe(NO3)3-nanoparticles on the surface. The catalyst is first reduced in flowing H2-gas at 900 oC, followed by CVD of nanotubes using pure methane as the feedstock. A porous alumina substrate coated with an iron/molybdenum catalyst [5] placed upstream from the samples was found to promote nanotube growth. After growth, Cr/Au alignment marks are patterned on the substrate using a standard electron-beam lithography process. Nanotubes are located relative to the alignment marks with an atomic force microscope (AFM). A second electron-beam lithography step establishes Cr/Au source and drain contacts to the nanotube for conductance measurements. The conducting silicon substrate acts as a third (gate) electrode. Conductance measurements were made in the linear response regime using an AC technique. Figure 1 (upper panel) shows an AFM topograph of the device. The thin curving nearly horizontal line is the nanotube, the large dark blocks are Cr/Au electrodes and alignment markers. The nanotube has a diameter of approximately 2.2 nm. The lower panel of Figure 1 shows the conductance of the device as a function of gate voltage. As previously observed before [1, 6] the semiconducting nanotube behaves similarly to a p-channel field effect transistor (FET). The characteristics of an FET allow us to calculate the mobility of the majority carriers (holes in a p-channel FET) using the slope dG/dVg of the linear part of the conductance vs. gate voltage curve as shown in Figure 1. For a nanotube FET this yields the following formula for the mobility μ: